The present invention relates to a slot reception synchronization circuit. More specifically, the invention relate to a slot reception synchronization circuit for a digital mobile communication system employing a TDMA (Time Division Multiple Access) communication system as communication system, which is employed in a digital cordless telephone, satellite communication and so forth.
The conventional digital mobile communication defines a time frame to be a basic frequency and performs communication by transmitting and receiving digital data signal employing a given period of time (time slot) assigned in the time frame.
Accordingly, a plurality of channels can be multiplexed on the same carrier by the time slot, it becomes necessary to adjust timings of respective communication systems so that mutual interference due to overlapping of the transmission signals at respective channels between the communicating systems will not be caused.
Therefore, a common time reference is provided for communication systems which perform transmission and reception. This is to establish synchronization with the distant system by setting a counter value indicative of time information to be taken by the time slot upon detection of a signal with a particular bit pattern in a reception signal (unique word) to a slot counter when the unique word is detected.
The conventional slot reception circuit comprises an input control circuit 10, a reception data shift register 11, a unique word detection circuit 12, a slot counter circuit 13 and a timing control circuit 14, as shown in FIG. 5.
The reception data input under control of the input control circuit 10 is received in the reception data shift register 11. The reception data shift register 11 is a shift register of m bits corresponding to the length of the communication slot data of the received data.
The unique word detection circuit 12 performs detecting operation for detecting the specific data pattern (unique word of k bits) from the input reception data independently of the reception data receiving operation of the reception data shift register 11.
The slot counter circuit 13 establishes the slot synchronization by the detection signal from the unique word detection circuit 12 and notice the establishment of the slot synchronization to the timing control circuit 14. The timing control circuit 14 performs timing control of the reception data through overall reception.
In the unique word detection circuit 12, exclusive NORs (EXNORs) of the reception data taken in reception data registers 12a-1 to 12a-k from the input control circuit 10 and predetermined k bits of the unique word pattern 12c are taken by exclusive NOR circuits 12b-1 to 12b-k, as shown in FIG. 6. The result of this operation is added in an adder 12d. When all k bits are matched, namely when the sum attained by the adder 12d becomes k, the unique word detection signal is output.
Such type of the slot reception synchronization circuit inputs the reception signal as serial input to the unique word detection circuit 12 which is independent of the reception data shift register 11, in parallel to the input operation to the reception data shift register, for detecting the unique word by detecting matching of all bits.
In this method, the synchronization is established by setting the counter value indicative of the time information to be taken at a timing where the all bits of the signal having the specific data pattern (unique bit of k pattern) are detected, as the initial value for synchronization.
Next, the slot counter circuit 13, in which the synchronization is established, enables input of the reception data to the reception data shift register 11 again at the timing corresponding to the timing of the leading end of the slot for receiving the reception data.
On the other hand, an example for detecting the unique word in the way different from the above-mentioned unique word detection method has been disclosed in Japanese Unexamined Patent Publication No. 3-78338. In the disclosed method, as shown in FIG. 7, a decoding circuit 20 and a unique word detecting circuit 21 are included.
As the decoder circuit 20, there is the decoder circuit employing a Viterbi decoding system as an error correction system. By inputting of the reception burst signal RD, the reception burst signal DRD decoded by the decoding circuit 20 is supplied to a demultiplexing portion (not shown) and also supplied to the unique word detecting circuit 21.
The unique word detecting circuit 21 comprises a unique word detecting circuit main body 22, an error rate prediction circuit 23 and a ROM 24. As shown in FIG. 8, the unique word detecting circuit main body 22 comprises a shift register 22a, a reference pattern register 22b and a comparator 22c.
The shift register 22a is responsive to input of the decoded reception burst signal DRD to convert the reception burst signal DRD into a parallel signal to output to the comparator 22c. The comparator 22c compares the parallel signal output from the shift register 22a and the reference pattern of the unique word from the reference pattern register 22b with taking a predetermined allowable error bit number 22d as a detection threshold value.
The result of comparison of the comparator 22c is output as a unique word detection signal UDS. It should be noted that, for the comparator 22c, a terminal for setting the allowable error bit number 22d is provided.
On the other hand, the error rate prediction circuit 23 inputs a parameter as a bi-product in the process of decoding of the reception burst signal in the decoding circuit 20 and derives an average value of the parameter in time series. This parameter is referred to as path metric.
The error rate prediction circuit 23 predicts the current error rate CS of a channel on the basis of the average value of the parameter in time series. It should be noted that a data indicative of the average value of the parameter in time series and the error rate is preliminarily obtained through experiments and stored in a memory (not shown) of the error rate prediction circuit 23.
The error rate prediction circuit 23 predicts the error rate CS on the basis of the stored data in the memory. Also, ROM 24 preliminarily stores an optimum allowable error bit number HS corresponding to the error rate CS.
When the reception burst signal is received in the slot reception synchronization circuit constructed as set forth above, the reception burst signal RD is decoded by the decoder circuit 20. The reception burst signal DRD decoded by the decoder circuit 20 is supplied to the demultiplexing portion and to the unique word detecting circuit 22.
At the same time, the parameter obtained in the decoder circuit 20 is input to the error rate prediction circuit 23. In the error rate prediction circuit 23, the average value of the parameter from the decoder circuit 20 in time series is calculated. From the average value of the parameter in time series, the current error rate CS is predicted. The error rate CS predicted by the error rate predicting circuit 23 is supplied to the ROM 24 as an address.
From the ROM 24, the optimum allowable error bit number HS corresponding to the error rate CS from the error rate predicting circuit 23 is read out. This optimum allowable error bit number is supplied to the unique word detecting circuit main body 22a and set therein. Namely, in the unique word detecting circuit main body 22a, the optimum allowable error bit number at the current channel quality is set.
By this, the reception burst signal DRD decoded by the decoder 20 is compared the optimum allowable error bit number HS with the reference pattern as the detection threshold value. Therefore, the unique word is detected under a condition where the failure rate of unique word detection and the erroneous detection rate of the unique word becomes minimum.
However, such conventional slot reception synchronization circuit, the unique word detection is performed independently of the reception data register. Therefore, it becomes necessary to initially establish the synchronization of the slot.
Here, the reception data latched at a timing of detection of the unique word is input to the reception data register, but no relationship between the unique word detecting position and the reception data shift register is taken.
Therefore, since the reception data is offset from the normal position, a pitch position correction for normalization is inherently required. Otherwise, in order to take the reception data from the leading end of the slot, the reception data should be abandoned upon detection of the unique word.
Also, in order to correctly receive the data, the data has to be again input to the reception data shift register from the beginning of the slot indicated by the slot timing at which the synchronization is established.
Furthermore, in detection of the unique word, since the conventional slot reception synchronization circuit does not allow any bit error of the unique word, the possibility of failure of detection of the unique word becomes high to make it difficult to perform stable slot reception.
As a solution for this, there is a method to improve the reception certainty by allowing a given number of error bits in the unique word in detection of the unique word. However, since the data of the reception data shift register and the data of the reference pattern register are directly compared by a comparator with an allowable error bit number, elements forming the circuit becomes increased to make the circuit complicate.